Model Your ADCs In Spice (Part 2)

When designing a system’s signal chain, lots of time is probably devoted to selecting the proper analog-signal driver for the successive-approximation register analog-to-digital converter (SAR ADC). Consequently, to preserve input-signal integrity and obtain the maximum performance from each system component, the focus shifts to the input buffer as well as the RC filter in front of the ADC. However, the …

Designing embedded SoCs using older resistive technologies

When designing an SoC with a generic 32-bit MCU based on 0.18um (180 nm) processes with flash and a rich suite of analog and digital IPs, the authors found that the pre-route engines from current EDA tool vendors are tuned for smaller transistor node sizes and are not very good at the larger 180 nm geometries. Here are the steps …

A brief primer on embedded SoC packaging options

With shrinking technology, voltage levels are being reduced, lowering noise margins required to enable a clean design from a signal integrity perspective. Higher operating frequency requirements further complicate design closure. Semiconductor packages are a quintessential piece of the signal integrity puzzle. This article addresses the basics of packaging such as types of packages and their advantages and disadvantages, future …