New JESD204B Interface Speeds And Simplifies ADC To FPGA Interconnection

Developers in communications and industrial/commercial digital applications often come across problems when implementing the connection between a high-resolution analog-to-digital converter (ADC) and an ASIC or FPGA. JEDEC has released a high-speed serial bus to increase productivity. Previously, connections used a low-voltage differential signaling (LVDS) differential bus. With up to 14 to 16 bits of parallel data from an ADC and …