New JESD204B Interface Speeds And Simplifies ADC To FPGA Interconnection

Developers in communications and industrial/commercial digital applications often come across problems when implementing the connection between a high-resolution analog-to-digital converter (ADC) and an ASIC or FPGA. JEDEC has released a high-speed serial bus to increase productivity. Previously, connections used a low-voltage differential signaling (LVDS) differential bus. With up to 14 to 16 bits of parallel data from an ADC and …

QSFP+ Transmitter-Controller Chipset Reduces Power Consumption

Thank you for recommending “”. Your recommendation has been successfully processed. Date Posted: October 04, 2012 04:11 PM Data centers are gradually adding 40-Gbit/s capability as their 10-Gbit/s traffic increases and aggregation needs expand. However, power consumption is inhibiting that growth. The MAX3948 laser driver-controller chipset from Maxim Integrated Products, though, provides four lanes of 11.3-Gbit/s laser driver capability …

Integrate Your Signals Before Digitizing Them

As an applications engineer for a company making configurable analog products, I occasionally get asked to provide a design to integrate a signal before digitizing it. In many cases, the people doing the asking are interested in the area under the waveform. Sometimes they just want to use the integrator to amplify a very small dc signal. They initially envision …