ASIC Architect – 32-bit RISC-V Microcontrollers

Own the architecture of a 32-bit RISC-V MCU family, from customer requirements to production silicon.

This is an architecture role with responsibility for the decisions that determine how a device behaves in the field: interrupt latency, memory access, synchronised sampling, motor control, security and reliability.

The devices target precision agriculture and industrial control, including motor drives, precision sensing and automation. They are designed for 10–15 years of operation in electrically noisy environments, across temperatures from -40°C to +125°C.

Adelaide, South Australia | Full-time, permanent | Hybrid, with lab attendance as required

The role

You will define the MCU architecture and guide its implementation through RTL, verification, physical design, tape-out and silicon bring-up. You will provide technical leadership to 4–8 design and verification engineers per program, with no direct reports.

• Define CPU subsystems, memory maps, interrupts, clocking, reset and power domains.
• Select and integrate RV32 cores, ISA extensions, PMP, interrupt controllers, debug and trace.
• Architect embedded flash or MRAM, ECC-protected SRAM, caches, tightly coupled memory and flash wait-state strategies.
• Specify AHB/AXI/APB interconnects, DMA and arbitration for predictable control-loop latency.
• Define high-resolution PWM with sub-nanosecond edge placement, complementary outputs, dead-time, fault trips and safe-state behaviour.
• Architect synchronised ADC sampling, encoder and resolver interfaces, and acceleration for field-oriented control at 20–100 kHz.
• Work with mixed-signal engineers on sensor front ends, including SAR and sigma-delta ADCs, programmable-gain amplifiers, comparators and digital filtering.
• Define industrial connectivity, including CAN FD, SPI, I²C, UART and Ethernet options where required.
• Own architecture decisions for secure boot, crypto, key storage, debug access, watchdogs and fault monitoring.
• Model performance, power and area, resolve trade-offs and support first-silicon validation and customer debug.

What you will bring

• 10+ years in digital ASIC/SoC development, including at least four years in an architecture or lead role.
• Architecture ownership of at least one MCU or embedded SoC taken through to production silicon.
• Deep knowledge of RV32 CPU subsystems, ISA extensions, CLIC/PLIC, PMP and RISC-V debug.
• Strong understanding of AMBA, DMA, memory hierarchies and embedded non-volatile memory.
• Architecture or design experience with motor-control peripherals and mixed-signal sensor front ends, including their timing and determinism requirements.
• Working knowledge of RTL, UVM verification, synthesis, STA, DFT and UPF-based low-power design.
• Performance or power modelling in C/C++, SystemC or Python, and clear specifications that engineers can implement and verify.
• A relevant engineering degree.

Also valuable

Industrial security standards; CAN FD, ISOBUS, EtherCAT, PROFINET or TSN; hands-on motor control or precision measurement; mature-node embedded-flash processes; AEC-Q100; FPGA prototyping; custom RISC-V extensions; and Arm Cortex-M migration experience.

Interested? Apply with your CV and a brief outline of an MCU or SoC you helped take to production, including the architecture decisions you owned.