Will LDE Stand Between You And Your Next Smart Device?

Mobility is the key driver for today’s consumer. Successful applications must provide technology integration, high bandwidth, and low power. Compared to 28 nm, 20 nm potentially provides upwards of 20% improved performance, 30% power savings, and a 50% area reduction that allows designers to place between 8 billion and 12 billion transistors on a single system-on-chip (SoC). 20-nm devices will fuel a new generation of smart phones, tablets, and other high-performance, low-power mobile devices. However, some technical challenges must be resolved before 20 nm is widely adopted.

From a custom IC design perspective, manufacturing complexity at 20 nm represents a seismic shift from previous process nodes. Why? Because of the emergence of the FinFET transistor for common usage, a multitude of very difficult and competing design rules, advanced lithography effects, and the need to approach the design from the beginning with an awareness of physical effects. At advanced process nodes, physical complexity explodes and circuit parasitics and mismatch in the analog components become so severe that designers will use more digital control circuitry and calibration where analog used to be sufficient.

The Complexity Of LDE

One of the most prominent aspects of manufacturing complexity is layout-dependent effects (LDE). At 20 nm, the layout context-what is placed near a device-can impact device performance by as much as 30%. No longer is it sufficient to characterize device performance in isolation. You must also consider what will be placed near that device. While LDE was an emerging problem at 28 nm, it is significantly worse at 20 nm, where cells are much closer together.

Layout-dependent effects require you to account for not only traditional device and wire effects, but also for the effects of devices and wires related to their surrounding environments. To analyze these effects, you must address such concerns as the distance of a gate to each edge of the diffusion, gate-to-gate separation, and the overall length of the diffusion. Any handcrafting of devices-including any folding, merging, abutting, and dummy insertion-all impact LDE and consequently affect device performance. And these effects are on top of a host of new physical design rules and new interconnect layers as well.

One form of LDE is called “well proximity effect.” Threshold voltage varies according to how close a device is placed to a well, due to the doping conditions of the diffusion layer (see the figure). In this example, we show how the threshold voltage (VTH) changes dramatically for a transistor as its distance to the well edge changes. Foundry rules provide no guarantee that the voltages will be as you expect them. As shown in the right side of the figure, if you used the default distance, your threshold voltage could be as much as 24 dB below what you expected.

The threshold voltage (VTH) changes dramatically for a transistor as its distance to the well edge changes, but foundry rules provide no guarantee that the voltages will be as you expect them.

Changes In The Design Flow

LDE has a powerful impact on the custom/analog design flow. It is no longer sufficient to create a schematic, pick a topology, run a simulation, and throw it over the wall to a layout designer. At 20 nm, circuit designers need to consider the layout context and simulate with LDE prior to layout completion. While this may sound paradoxical, it is possible with the right tools and methodologies.

In an LDE-aware design flow, pre-layout sensitivity analysis tools will identify devices that are sensitive to LDE. Context-driven placement and optimization will then predict how different cells are going to interact and how the layout context affects timing and power. But most importantly, circuit and layout designers have to learn to work together with a much higher level of collaboration.

Certainly, LDE is not the only challenge at 20 nm. Because the resolution of a photo-resist pattern begins to blur around 45 nm, double patterning will be needed for nearly all 20-nm designs. Double patterning splits the design layers with structures that are too close together into two separate masks. Each mask is separately exposed so the wafer reflects what was originally drawn.

Other challenges include complex design rules, new local interconnect layers, device variation, and the potential use of a new type of transistor-FinFETs. As a result of manufacturing complexity, foundries are expecting customers to go through a whole set of new verification steps before receiving the customer’s GDSII file for manufacturing.

The Future Of 20-nm Technology

The key to a successful 20-nm custom design methodology is the continuous exchange and analysis of information between the front end and the back end. To facilitate cross-communication, the circuit designer will need to quickly analyze a layout of critical nets and devices to get an understanding of the layout-dependent effects on the circuit. This process will include placement, routing, the use of dummies, and complying with new placement and routing rules.

Extraction, design for manufacturing (DFM), and physical verification for advanced nodes can no longer be only a signoff step. Designers must be able to efficiently call signoff verification engines at any time during design to provide immediate signoff-quality feedback throughout the design and implementation phases.

Consumers are demanding low-cost, low-power mobile solutions that will require new 20-nm SoCs. 20-nm collaboration has been underway for several years, and new design solutions and methodologies are emerging. As a result, 20-nm technology will very likely show up in your next smart device-and just in time. We’re already working on 14 nm, 10 nm, and even more advanced technologies.