250-Msample/s 16-Bit ADCs Incorporate Fast JESD204B Interface

With the release of JEDEC’s JESD204B serial data interface, designers are abandoning the 14- to 16-bit parallel differential low-voltage differential signaling (LVDS) connections from analog-to-digital converters (ADCs) to FPGAs, DSPs, or some ASICs. This reduces the number of lines and lengthens the runs for a simpler circuit. Recently, Texas Instruments adopted the JESD204B interface for its 16-bit ADS42JB69 ADC. The …

New JESD204B Interface Speeds And Simplifies ADC To FPGA Interconnection

Developers in communications and industrial/commercial digital applications often come across problems when implementing the connection between a high-resolution analog-to-digital converter (ADC) and an ASIC or FPGA. JEDEC has released a high-speed serial bus to increase productivity. Previously, connections used a low-voltage differential signaling (LVDS) differential bus. With up to 14 to 16 bits of parallel data from an ADC and …

Tegra 3 COM Weathers Harsh Industrial Applications

Nvidia’s Tegra 3 multicore system-on-chip (SoC) is well known for powering smart phones and tablets, but its powerful, compact architecture makes it inviting for industrial applications as well. Kontron’s ULP-COM-SAT30 is host to a 1.2-GHz Tegra 3 in a compact 82- by 50-mm, Ultra-Low-Power Computer-on-Module (ULP-COM) form factor (see the figure). Kontron’s ULP-COM-SAT30 hosts a 1.2-GHz Nvidia Tegra 3 …