November 05, 2013
Slack time becomes very important when you are connecting an input to a system (or part of a system) that uses a different clock (including no clock at all).
Last time I talked a bit about flip flop set up and hold times and how synthesis tools compute the slack time to help route complex synchronous circuits. There is at least one other place where this becomes very important and that’s when you are connecting an input to a system (or part of a system) that uses a different clock (including no clock at all).
A common example would be a D flip flop input connected to a push button switch. The switch could change state at any time, including inside the critical time around the flip flop’s clock edge. This can push the flip flop into metastability — it can’t decide if the output should be a one or a zero. It may oscillate, or it may take on an indeterminate illegal value and may eventually stabilize well beyond the stated output delay time for the flip flop. There are other things that can push a flip flop into a metastable state. For example, a short clock pulse can have the same effect.
Of course, you can generally control the length of the clock pulse. You can’t control the timing of an external pushbutton. Well, not exactly, anyway.
What you can do is use a chain of multiple flip flops to ensure that the rest of your circuit will (probably) never see a metastable output. Of course, this also introduces a delay corresponding to the number of flip flops in the chain.
I say probably because there is always some chance that not only will the first flip flop hit the exact timing required to go metastable but that the second one will also. The more flip flops you add to the chain, the less likely you will have a problem but the higher the delay between input and the output of the synchronizer. Usually two stages are sufficient, although in critical applications you may need to do some math to prove that to your satisfaction.
Synchronous logic is fascinating and without it developing anything other than trivial logic circuits would be very difficult. However, things like metastability and set up times can lead to problems if you don’t dig under the abstractions we use to make things easier to understand.
If you want to experiment with building digital logic, any of the FPGA toolsets (for example, ISE from Xilinx or Quartus from Altera) will let you build logic (using schematics or a definition language) and simulate it. There is a bit of a learning curve, though, and lots to install.
If you want something simpler in your browser, have a look at Digital Workshop or LogicSim. There are doubtlessly many others, and even more if you are willing to download and install something. Then again, if you climb the learning curve to learn FPGA tools, you’ll be ready to realize your designs in hardware when you are ready.