In the race to achieve high design performance and stringent power requirements, the VLSI world is moving quickly down the scaling curve to process technologies that enable transistor fabrication at smaller and smaller geometries: 40nm (C40), 28nm, 20 nm and so on.
As we go down the technology nodes, a lot of new design variables comes into picture, causing our previous assumptions to fail. This has the result of forcing the use of more timing signoff corners to take into account their variations at different PVT (Process Voltage & Temperature) values.
For example, we may have as many as 16 timing sign off corners at C40, thus drastically increasing the turnaround time for the SOC implementation and closure.
In this article we describe what we have done to come up with a way to reduce the timing signoff corners through a better understanding of the smaller geometry variations across multiple corners and how it affects equally good silicon quality. Our analysis indicates that this can reduce the design cycle closure time significantly.
Accurate Timing Analysis with Corner Definition
An SOC mainly comprises of millions of sequential elements with combinational cells connected through metal nets in between, which generates a number of timing paths. For an SOC to work properly, all the timing paths have to met certain special timing checks like setup, hold (or any other race condition) etc.
Figure 1: An example of a timing path
Suppose you want an SOC to work at some particular PVT conditions defined by specific Process Voltage & Temperature range values (Figure 1 above). Temperature range comes from the application requirement.
The usual temperature range can be as extreme as -40 C to 150 C.
Voltage regulator specs are used to derive the SoC constraints factors in the other voltage drop effects across the SOC voltage range (for example, 1.08V to 1.32V).
The process which determines the quality of silicon doping has a strong dependency on the manufacturing capabilities of the silicon fabrication units.
Depending on the PVT conditions, gate delays and net delays can vary. Silicon designers need to ensure that the SOC should work across all the PVTs. This can be done by checking the timing requirements on all the timing paths at different PVT conditions.