October 07, 2013
Verilog is decidedly schizophrenic. There is part of the Verilog language that synthesizers can commonly convert into FPGA logic and then there is an entire part of the language that doesn’t synthesize.
Call me Al. Some years ago — never mind how long precisely — having little or no money in my purse, and nothing particular to interest me, I learned how to program computers using assembly and FORTRAN. (I apparently also read Moby Dick somewhere along the way.) After a few years I learned to program in PL/I (that last character is a Roman numeral one, so that’s pronounced PL-one not PL-eye). What struck me about PL/I was that almost no one used all of it. IBM had developed the language to replace FORTRAN and Cobol and so it had features that were aimed at both types of developers. As a FORTRAN guy, I almost never used some features and I’m sure the Cobol guys didn’t use some of mine.
I find the same thing happens with Verilog, but for a different reason. Verilog is decidedly schizophrenic. There is part of the Verilog language that synthesizers can commonly convert into FPGA logic and then there is an entire part of the language that doesn’t synthesize. I do use a small amount of code that doesn’t synthesize when writing test benches, but mostly I just figure out how to write test code using the synthesizable subset of Verilog.
Of course, different synthesizers, in theory, could handle different constructs, so your mileage may vary. The other day, I was reading someone else’s test bench and ran into Verilog user-defined primitives (UDPs). I dimly remembered that these existed, and wondered why I didn’t use them myself. I checked, and sure enough my usual synthesizer doesn’t handle them.
There are two types of UDPs: combinatorial and sequential. As you might expect, the combinatorial is just logic and the sequential has a clock-based flip flop component. Here’s a UDP that implements an XOR gate with an active low enable pin:
primitive ngated_xor(z,a,b,en_n); output z; input a,b,en_n; table // a b en_n z 0 0 0 : 0; 0 1 0 : 1; 1 0 0 : 1; 1 1 0 : 0; ? ? 1 : 0; endtable endprimitive
You can probably guess that the ? entries mean any value (0, 1, or x). You can create these just like you’d create a normal primitive like an and gate:
ngated_xor gxor1(result, inA, inB, oe_n);
At this point, you have to wonder why this is interesting. You could get the same result (and synthesize it) with, say, a case statement or using a collection of gates. However, next time I’ll talk about primitives that have state and can respond to signal edges as well as levels.
Perhaps like PL/I, I don’t really need to use all the Verilog features. But it is still interesting to learn all that you can about your tools. I’ll talk about sequential primitives next time. Meanwhile, if you want to wax nostalgic about PL/I, you might find the Iron Spring compiler for Linux interesting.