Model Your ADCs In Spice (Part 2)

Downs168x144When designing a system’s signal chain, lots of time is probably devoted to selecting the proper analog-signal driver for the successive-approximation register analog-to-digital converter (SAR ADC). Consequently, to preserve input-signal integrity and obtain the maximum performance from each system component, the focus shifts to the input buffer as well as the RC filter in front of the ADC.

However, the switched capacitive load presented by the ADC may prove difficult for the buffer. Using a buffer with limited unity gain bandwidth (GBW) or the wrong type of capacitor in the RC filter will likely compromise the conversion results.

A very simple model1 could be used in Spice to simulate a SAR ADC’s input stage (see “Model Your ADCs In Spice, Part 1”). It addresses the main concern of modeling the ADC input load as board-level and system-level designers can simulate drive circuitry and verify its operation before going to board fabrication.

While the ADC input signal driver gets its fair share of attention, less effort is typically put forth to properly understand the driving requirements for the reference input pin. Modeling the signal input alone allows for building a very simple model. Adding the reference input presents some interesting challenges, though.

In the capacitive conversion network of a typical SAR ADC, switch SA is closed and SB is switched to the input voltage (VIN) during sampling mode (Fig. 1). The remaining switches are turned to the common bus (B). During hold mode, switch SA is opened while the individual bit switches become connected to ground.

1. This SAR ADC is based on charge redistribution.

Subsequently, the conversion process connects each bit capacitor to the reference while the other switches remain connected to ground. Charge on the capacitor array gets redistributed at each step, placing a load on the reference. The state of the capacitor array is a function of the decision made by the comparator during the first bit test. Each bit test that follows represents a function of the preceding bit test. The voltage (VC) depends on which capacitors are set to VREF and which are set to ground.2

The comparator can only make the proper decisions if the reference voltage is stable and accurate. Requirements for settling time are much more demanding for the reference input pin. That’s because the main system clock drives the switching between capacitors, and the voltage must settle to within the accuracy required in the span of each clock cycle.

Similar to the ADC input, high impedances in series with the reference interact with this current to cause the voltage on the reference pin to change (Fig. 2). The top curve (trace R1) represents the start of an acquisition signal, which is the trigger signal received by the converter to sample the input signal. Then, after five clock cycles (for this particular converter), it initiates a new conversion.

2. The voltage-reference input draws current during the conversion cycle. This current, along with the source impedance of the reference and buffer circuitry, causes spikes to occur on the reference input. These spikes must settle within the bit decision time of the converter. Otherwise, the conversion result will be incorrect.

The bottom trace in Figure 2 represents the signal captured on the ADC’s reference input. It shows the charge spikes that appear on the ADC’s reference input pin during conversion. This figure uses the technique of an added resistor (like the case with the ADC input signal in Part 1)1 to amplify the process and show typical waveforms for driving conditions. Here, the added resistor is selected to show proper settling of the reference input voltage during every bit decision.

Two main spikes follow the start convert pulse in the upper trace. The first spike occurs at the beginning of the conversion cycle, while the second materializes when there’s scaling at the capacitive conversion network. It’s important to note that after every new clock, the reference voltage returns to the initial value before the next clock. This ensures the internal comparator is making proper decisions and preserves accuracy at the final digital output result.

An incorrectly designed drive circuit will generate different results (Fig. 3). Following the sampling command and five clock falling edges, the ADC’s reference input pin demands different amounts of charge, depending on the bit decision. The signal was captured with an oscilloscope’s low capacitive probe, which senses the voltage drop across a resistor between the ADC reference input pin and the reference source output (an RC filter).

3. An incorrect drive circuit doesn’t allow the reference to settle to the required accuracy within the converter’s bit decision time, causing erroneous results.

For this example, an RC filter was used in front of the ADC reference input pin, which was designed without following the guidelines given in the literature.3-6 Thus, it led to the filter’s time constant being too big. Therefore, during the conversion time, the reference voltage doesn’t return to its initial value before the end of the clock cycle. This results in ADC output data that doesn’t properly represent the input analog signal and ultimately compromises system accuracy.

Spice Model

To model the load presented by the reference pin, we can create a model using TINA-TI7 that’s based on the schematic shown in Figure 1 (Fig. 4). This is just one of several different ways to implement a charge-redistribution SAR ADC.

4. In this Spice model (based on the circuit in Figure 1), the VCSPDT blocks realize the switches and the controlled-source block (CS1) implements an ideal comparator.

One difficulty associated with the TINA-TI model is that you’re building the entire ADC. To do it properly, you need to model the SAR logic. That was not done in this case. However, seeing the interaction between the reference input and the captured signal input voltage requires this level of complexity.

This model implements only three bits of what would be a 16-bit converter. Piecewise linear (PWL) voltage sources control the switches. To illustrate, the netlist of the switches (Fig. 5) and the PWL source control list for the first bit test (Fig. 6) are provided.

5. The Spice netlist for the VCSPDT block uses two voltage-controlled switches.

6. Shown is a control table for piecewise linear source BitTest0, which controls the switch during the sample period (0 to 1µs) and then the bit test cycle (1.25 to 1.49 µs).

Simulation of the circuit in Figure 4, with low impedances on both the signal and the reference voltage inputs, reveals somewhat surprising results (Fig. 7). For instance, the instantaneous current drawn by the reference input is on the order of tens of milliamps! Still, with low external impedances, the reference voltage recovers and stabilizes quickly, ensuring that good bit decisions can be made.

7. Simulation results are given for R3 = 10 Ω. While the instantaneous reference current is significant, the low impedance allows the reference voltage (VREF) to settle quickly, allowing for good bit decisions to be made. The voltage reference error, in LSBs, is shown in the middle (yellow) trace.

It’s instructive to look at the change in reference voltage in terms of the converter’s least significant bit (LSB). If this was a 16-bit converter, the reference voltage would be disturbed by almost 4000 codes, and yet recovers within the 250-ns bit test time to well within a half-LSB.

Changing R3 in Figure 4 to 10 kΩ and simulating again yielded the waveforms shown in Figure 8. The reference voltage behaves similarly to what we saw in Figure 3, and it doesn’t recover within the 250-ns bit decision time.

8. When R3 = 10 kΩ, the reference voltage can’t recover during one bit decision clock cycle. In this case, it only gets to within 12% of its correct value-an eye-opening error of approximately 8000 codes.

In both cases, the circuit really wasn’t what would exist in a real circuit. Usually, at the very least, there would be some external bulk capacitance from the reference input to ground. More sophisticated circuits, like that shown in Figure 1, are also used to filter noise.8 When a 10-µF capacitor is placed from VREF to ground, changes in VREF are well within a half-LSB (Fig. 9).

9. Simply placing a 10-µF capacitor from the VREF input to ground can improve behavior, even with a large R3.

High-resolution ADCs sometimes require buffering in addition to filtering the reference.9 These circuits often have stability concerns because the amplifiers drive significant capacitance.

Overall, Spice and models like those presented here can help in the design of a robust and accurate reference circuit for your ADC. So far in this series, I’ve presented models of SAR ADCs. The next part will look at some of the concerns with modeling delta-sigma and pipeline converters for system design.


  1. Downs, R., “Model Your ADCs In Spice (Part 1),” Electronic Design, June 15, 2012.
  2. Kugelstadt, T., “The operation of the SAR-ADC based on charge redistribution,” Analog Applications Journal, Feb. 2000, Texas Instruments.
  3. Downs, R., “Signal Chain Basics (Part 33): Use an op amp to drive a precision ADC,” PlanetAnalog, Sept. 1, 2009.
  4. Downs, R. and Oljaca, M., “Designing SAR ADC Drive Circuitry – Part 1 of 3,” EnGenius, Feb. 21, 2005.
  5. Downs, R. and Oljaca, M., “Designing SAR ADC Drive Circuitry – Part 2 of 3,” EnGenius, Oct. 2006.
  6. Downs, R. and Oljaca, M., “Designing SAR ADC Drive Circuitry – Part 3 of 3,” EnGenius, March 12, 2007.
  7. Download a free version of TINA-TI:
  8. Stitt, M., “Voltage Reference Filters,”Application Note (SBVA002), Texas Instruments, 1990.
  9. Baker, B. and Oljaca, M., “How the voltage reference affects ADC performance, Part 3”, Analog Application Journal, (4Q2009), Texas Instruments