IBM Still Major Source of Chip Innovation Despite Exit Rumour

IBM’s Semiconductor Division and Intel have been two of the primary drivers of advanced CMOS development for nearly fifty years.

Although Intel has usually been first to market with a new technology node, IBM has continued to be a major source of innovation in advanced CMOS technology over the past decades. IBM achieves their impressive R&D record despite only having about $2 billion in semiconductor revenue, as compared to Intel’s $50 billion. One secret to IBM’s success is their partnerships with other major players.

Despite rumours that IBM might exit the semiconductor business, IBM’s East Fishkill, NY, fab is one of the primary development centers, along with Albany Nanotech, for the Common Platform technology, a partnership between IBM, Samsung, and GlobalFoundries.

Chipworks has analyzed the evolution of IBM CMOS technology over the past decade. A particular focus for Chipworks has always been the transistor structure, which has become of increasing interest recently with the appearance of high-k metal gate (HKMG) technology.

IBM PPC970FX 90 nm NMOS Transistor (Source: Chipworks)

IBM PPC970FX 90 nm NMOS Transistor
(Source: Chipworks)

The 90 nm IBM PPC970FX
The 90 nm IBM PPC970FX was analyzed by Chipworks in 2004. The 970 PowerPC family of chips was apparently the result of a short-lived collaboration between Apple and IBM. The PPC970FX was built on silicon-on-insulator (SOI) wafers using a 12 metal process, including a single level of single damascene copper for metal 1 and nine levels of dual damascene copper for metals 2 through 10. A top aluminum-based metal was used for the bond pads, while a tungsten-based metal was used for metal 0 local interconnects. The active silicon SOI islands are isolated from the substrate by a buried oxide (BOX). Fluorosilicate glass, oxide, and nitride dielectrics were used for the back end of line (BEOL) process. Unlike the 90 nm offerings of other vendors at the time, carbon-doped low-k dielectrics were not used by IBM.

The transistors used on the PPC970FX were formed with polysilicon gates with a 0.35 µm contacted gate pitch (CGP). A nitride liner is used over the transistors and serves to provide tensile strain for the NMOS transistors to increase the electron mobility in the transistor channel. The NMOS sidewall spacer (SWS) was markedly thinner than the PMOS SWS, which further increased the strain applied to the NMOS transistors as compared to the PMOS transistors. The transistors were silicided with cobalt; however, no embedded epitaxial SiGe source/drain was used in the PMOS transistors, even though Intel had already introduced that technology at that time.

Microsoft X02046 90 nm PMOS Transistor (Source: Chipworks)

Microsoft X02046 90 nm PMOS Transistor
(Source: Chipworks)

The 90 nm Microsoft X02046
The Microsoft Xbox 360 contained a customized IBM PowerPC processor, the X02046, which was designed jointly by Microsoft and IBM, and manufactured by IBM at their East Fishkill 300 mm foundry, using IBM’s 90 nm SOI technology. Curiously, at that time the processors used by the three main game manufacturers, Microsoft, Sony, and Nintendo, were all based on similar IBM technology. Chipworks published an analysis of the Microsoft X02046 processor in 2006. The X02046 was fabricated with a 10 metal process. The major difference between the X02046 and the PPC970FX was the introduction of dual stress liner (DSL) technology, where a tensile liner was applied to the NMOS and a compressive liner to the PMOS. In addition, the X02046 featured carbon-doped, low-k dielectrics.

IBM Power6 65 nm PMOS Transistor

IBM Power6 65 nm PMOS Transistor

The 65 nm IBM Power6
IBM continues to offer foundry services at 90 nm and 65 nm for bulk CMOS, and 45 nm and 32 nm on SOI and other speciality services; however, IBM retains its most advanced SOI technologies for their high-end Power server products. The processor chip in the IBM Power6 server analyzed by Chipworks was built using a 65 nm SOI process that featured dual stress liners to enhance both the PMOS and NMOS device performance. Eleven layers of metal with low-k dielectrics were used to fabricate the device. The transistors feature NiPt silicided polysilicon gates with a minimum contacted gate pitch of 0.25 µm, corresponding to the expected 0.7X shrink from the 90 nm node. NiPt silicide has a lower sheet resistance than CoSi. Again, we see no embedded SiGe in the PMOS devices.