October 30, 2013
Any of the flip flops that require a clock have two key parameters that are crucial to understand if you are going to do any sort of digital logic design: setup time and hold time
A few weeks back I was talking about simulating flip flops with Verilog user-defined primitives. Of course, there are plenty of ways to synthesize flip flops ranging from vendor-supplied instances to inferring a flip flop from an always statement to blocking assignments. If you want to get really old school, you can get flip flops as standalone gates, make them out of simpler gates, or even build one out of transistors (or even vacuum tubes).
You are probably aware of the different kinds of flip flops: the D, the T, the JK, the SR, and the many variants thereof. But any of the flip flops that require a clock have two key parameters that are crucial to understand if you are going to do any sort of digital logic design: setup time and hold time.
Consider a classic D flip flop. It takes a clock and a D input. When the clock has a rising edge (or a falling edge, depending on the flip flop), the output takes on the value of the D input at that time. At any other time the D input can change and the output doesn’t change. Simple, right?
Like most things in computers and electronics, that is a simple abstraction. Wires are not perfect. Insulators leak current. Resistors exhibit inductance. Most of the time, however, we can treat wires and insulators as if they are perfect and can ignore inductance in resistors. The same holds true for the simple D flip flop abstraction. It is good enough for most common cases. But it breaks down if you look at it in too much detail.
Flip flops work by feeding their output back to their inputs. It is like have a pump that circulates water around in a loop. When the clock edge occurs, the pump gets rid of the previous contents of the loop and takes in whatever is waiting at the inlet. This is a bit oversimplified, but it is actually what is happening inside of a flip flop, more or less. The output keeps feeding the input until the clock forces a different input which causes a new output.
The problem is what happens right at that clock edge. If the D input is stable — that is, it doesn’t change — then there’s no problem. The clock edge causes the flip flop’s circuit to generate a new output. What happens if the D input changes just before the clock edge occurs? What happens if it changes just after the clock edge?
If the D input is changing just as the edge occurs, you may have a setup time violation and the output of the flip flop can be undefined. For example, a 74LS74 (a discrete TTL flip flop) has a 20ns setup time. If the D input changes within 20nS of the clock edge, the device won’t guarantee proper operation.
The hold time represents how long the input has to stay stable after the clock edge for proper operation. The 74LS74 has a 5nS hold time. A typical circuit will have a series of flip flops connected by some combinatorial logic (that is, or gates, and gates, and inverters). The network of connecting logic will have some amount of delay as the signal propagates through them. The wiring will also have a small amount of delay, as well.
That delay is good, up to a point. If all the flip flops saw the input signals change at the same time, synchronous logic wouldn’t work! In some cases (like two flip flops connected directly together) this could be a real concern. Logic synthesis software will introduce delay to make sure the setup time is exceeded. The difference between the actual setup time and the desired setup time is called setup slack. A positive number means the signal isn’t getting to the input too fast.
You can also compute hold slack the same way. It is harder to fix hold slack. If an input isn’t held long enough, you may need a slower clock. Think of it this way: The signals from one clock edge have up to the time of the next clock edge to get to their next input. A slower clock will allow for a longer set of delays between flip flop inputs.
When a synthesis tool can find a solution for a given clock frequency that has positive slack for both setup and hold times, your design has met timing closure. The tools take many other factors into account. For example, the clock won’t get to all flip flops at exactly the same time (clock skew), and that will also affect setup and hold calculations. However, the tools can’t always exactly figure out the correct slack. Your design might have inputs that can’t change at the clock rate, for example. Sometimes you have to identify problem areas for the tool to get good results.
There is one other issue that occurs with flip flops having to do with setup and hold time: metastability. This is a problem when you have input to a design that doesn’t obey the system clock. I’ll have more to say about that next time.