Clock-jitter performance has become a top priority among clock, analog-to-digital controller (ADC), and power-supply manufacturers. Why? Simply, it interferes with the performance of digital circuits, particularly high-speed ADCs. High-speed clocks can be quite sensitive to input power “cleanliness,” though quantifying the relationship takes some effort.
New lines of regulators (predominantly low-dropout regulators, or LDOs) coming from voltage-regulator manufacturers promise higher power-supply rejection ratio (PSRR) specifically for powering precision clocks and sensitive circuits. In addition, recent articles reveal that the performance of the clock and subsequent high-speed ADCs can be quite acceptable when replacing the linear regulator with a switching regulator.1
Figure 1 shows a test setup for measuring clock phase noise and jitter. The clock is connected to the Picotest J2180A preamp to connect the high-impedance clock to the 50-Ω spectrum analyzer. The J2130A dc bias injector eliminates any potential dc voltage at the spectrum analyzer, which could overload the spectrum analyzer ADC.
Noise Paths To The Clock
The most fundamental relationship between clock jitter (TJ) and power-supply noise, NV can be defined by:
This relationship clearly shows the need to establish the clock jitter’s sensitivity to the power-supply noise as a function of frequency. It’s also important to understand the frequency range of interest, which generally extends to the ADC’s highest signal frequencies. Not all clocks are similar. In fact, some of the newer, higher-throughput clocks feature built-in high-performance linear regulators, phase-locked loops (PLLs), and jitter cleaners to reduce the sensitivity of the clock’s performance to power-supply noise.
Defining the power-supply noise requires at least three terms. However, there are several less prominent paths, too.
Equation 2’s relationships show the three major noise paths to the clock:
The first represents the noise presented at the input to the linear regulator, which is reduced by the regulator’s PSRR. This illustrates why so many manufacturers are fixated on improving the high-frequency PSRR of next-generation LDOs. The second noise path goes from the regulator’s internal noise to the regulator output. The third and less frequently discussed path emerges from current variations at the output of the linear regulator interacting with the impedance present at the regulator’s output, which is also the input power to the clock. This becomes quite significant if other dynamic loads connect to the same regulator.
One of the more complex issues associated with measuring clock performance is determining and then presenting the clock with appropriate noise voltages and currents. Some recently published articles on the subject specifically address this major shortcoming.2
This article demonstrates the effects of, and sensitivities to, these noise paths. It also provides some general guidelines for streamlining the power requirements to optimize the performance of the clock.
Measuring The Noise
Examples discussed in this article use a low-cost, off-the-shelf, 3.3-V, 125-MHz CMOS surface-mount clock. The relatively low frequency is fairly common and inexpensive, and the sensitivity is high enough to be representative of typical present day ADC circuits.
This CMOS oscillator is designed to operate into a 1-MΩ 15-pF load. Therefore, a 10X scope probe is employed along with a Picotest J2180A wideband preamplifier to convert the high-impedance probe to the 50-Ω input of the Agilent N9020A signal analyzer that’s measuring the clock noise. A J2130A dc bias injector operates as a dc block to eliminate the possibility of overloading the analyzers sensitive front-end circuitry or ADC.
Also discussed is the popular LM317 linear regulator, as well as a custom-designed voltage regulator, which provide power to the clock for the test. The testbed is a Picotest Voltage Regulator Test Standard (VRTS) kit. It enables simple connections to the inputs and outputs. Also, it supports interchangeable linear regulators for comparative measurements.
Looking at test results, the large 2-MHz signal from the LM317 is due to the regulator’s control loop and the impedance of the wall adapter, including the impedance of its output wires and connector (Fig. 2). The custom-designed regulator, offering 50-dB PSRR at 2 MHz and a much higher bandwidth, rejects most of this input noise signal.
If a benchtop supply (connected to the VRTS board with common 18-in. banana test leads) replaces the wall adapter, it significantly degrades the performance of the clock (Fig. 3). While inductance for the test leads and the wall adapter both measure approximately 1 µH, the bench supply impedance and test leads result in a much higher Q (and, in fact, oscillation occurs as evidenced by the appearance of the 2-MHz signal and its harmonics). Adding a 0.47-µF ceramic capacitor at the input to the regulator greatly reduces the input impedance at 2 MHz. The resulting jitter drops to 2.8 ps.
Replacing the wall adapter with a bench supply and input-capacitor decoupling greatly reduces the clock jitter. The clock’s sensitivity to the input and output impedances of the power circuitry can be demonstrated with a Picotest J2111A current injector. The injector provides a narrow current pulse that can be connected at either the input or output of the linear regulator, providing external transient stimulus. The narrow pulse is rich in harmonics.
For the demonstration, the J2111A current pulse is connected to the input of the linear regulator (Fig. 4). The wall adapter’s finite impedance transforms the current signal to a voltage spectrum, which then passes through the linear regulator via PSRR and on to the clock, producing jitter. Adding the capacitor reduces the impedance, and therefore, the noise voltage to the clock. It’s important to ensure that the capacitor doesn’t resonate with inductors, beads, or other circuit reactances that can result in high Q resonances. Otherwise, the noise level would increase at the clock.
In a different test, the J2111A current pulse is connected to the output of the linear regulator (Fig. 5). Once again, the finite regulator impedance transforms this current into noise voltage that’s passed on to the clock, adding jitter. The high-bandwidth custom regulator features much lower impedance below 1 MHz as evidenced by the reduced spur amplitudes, while the high-bandwidth regulator displays a jitter-inducing resonance near 1.5 MHz. Both regulators have a resonance near 5 MHz that also contributes to jitter.
The displayed average noise level (DANL) ensures the tests’ validity and determines the measurement limitations (Fig. 6). The noise floor is approximately –143 dBc and the corresponding jitter is 441 fs.
Through all of these simple measurements, it becomes clear that clock jitter is sensitive to noise levels present at the clock’s power-supply terminals. It also demonstrates that the finite non-zero impedance levels at the input and output of the regulator contribute significantly to the clock jitter as a result of an external stimulus. While the linear regulator’s PSRR is the key term in clock jitter sensitivity, all other terms also must be considered.
Consequently, a few design guidelines are deemed essential when providing power to a clock or low-noise amplifier (LNA):
- Minimize the impedances at both the input and the output of the regulator feeding the clock. This diminishes susceptibility to external signals.
- Maximize the regulator’s PSRR to attenuate input signals as much as possible.
- Ensure that no phase discontinuities exist in the impedance (high Q resonances) at either the regulator input or output. These impedances should always be measured over the entire frequency range of interest.
- Be careful when using RF beads to isolate the oscillator from external noise. Beads can be quite inductive and may cause counterproductive phase discontinuities. While the bead will attenuate noise from the regulator, it can also increase the impedance, making the clock more susceptible to load-current-induced jitter.
- Don’t operate any other dynamic equipment from the same regulator as the clock. The stability or phase discontinuities of any other regulators that share a common input with the clock’s regulator could result in crosstalk. This, in turn, will introduce another path to clock jitter.
- Neu, Thomas, “Power-Supply Design For High-Speed ADCs,” TI App Note, Analog Applications Journal, 1Q 2010.
- “Power supply challenges in data and voice communication systems,” Gregory Waterfall, Masashi Nogawa and Dheepan Sundaram, Texas Instruments ECN 04/19/2012; “Supply Noise Effect on Oscillator Phase Noise,” Texas Instruments Application Notes SLWA066 Nov. 2011.