Building in RTOS support for safety- & security-critical systems

This last part in a four part series presents an example project concept that is based on an FPGA embedded hard core processor implementation. It addresses a complex design implementation that is beyond the scope of this series. Rather, the intent is to show a potential real-world advanced design example and discuss some of the factors that must be addressed in order to implement the system.

As an aid to the reader, application notes and reference papers are called out. These documents provide a lower-level implementation detail. For a broader understanding of the technology utilized in this example review of datasheets and user guides is appropriate.

For the purpose of this example, the result of the architecture and processor evaluation is Xilinx’s XC4VFX20 component. This FPGA includes a 405 PowerPC processor, tri-mode Ethernet block, embedded memory and DSP s ***a***lices.

Our FPGA-based projected system requirements include a PCI bus interface, a 10/100 Ethernet connection, an external DDR memory controller for access to processor memory and an external Flash memory controller for access to stored program memory.

Additionally, the system will support an I2C interface, an SPI interface, an RS-232 UART implementation and access to external switches and LEDs via GPIO signals. The system will also support a DSP function, and custom circuits. Figure 14.4 below illustrates the proposed system architecture.

Building in RTOS support for safety- & security-critical systems

Figure 14.4. Processor concept example

Xilinx’s system tool for implementing the embedded processor within the FPGA is the embedded development kit (EDK). EDK integrates the system, hardware and software tools together into one package. By following the automated flow, an evaluation board may be used as a starting point for the project. The evaluation board chosen should include as many equivalent features as possible in common with the final target application. Availability of the right evaluation board can help reduce design schedule and risk.

While it may not be possible to obtain an evaluation board with exactly the mix of peripherals and exact FPGA component desired, it should be possible to find a board with a similar part from the targeted FPGA device family. For this example, we will obtain a board with a XC4VFX12 component. Most evaluation boards include DDR memory, the 10/100 Ethernet PHY, dip-switches, LEDs and an RS-232 interface. The evaluation board should also support cable configuration and processor debug via a JTAG header.

Once the evaluation board has been obtained, the EDK should be used to configure the evaluation board. This process involves stepping through the automated flow. An example automated project configuration flow follows:

1)  Select a new project using the automated flow
2)  Select the evaluation board that was obtained
3)  Select the processor (for this example, the PowerPC processor will be selected)
4)  Enable the processor core features (for this example, the processor core frequency will be 200 MHz, the bus frequency will be 100 MHz, cache-enabled, and a JTAG interface selected for debugging)
5)  Select the device to be used
6)  Big endian format is preferred for TCP/IP implementations
7)  Device peripherals, addresses and modes of operation (for this example, DDR memory, Flash, Ethernet, and RS-232 are selected and configured)

After these steps have been completed an initial project may be built and the FPGA configured. Using this project, initial development of the software can begin. This project is then stored and the configuration of the PCI, SPI, I2C, and timer can be performed. The configuration of these devices includes connecting each device to the processor bus.

The selection of the processor core will heavily influence the implementation of the processor bus. The processor bus is responsible for supporting communication between the processor core and its peripherals. The bus supported by EDK for the 405 core is an implementation of IBM’s CoreConnect bus structure. The bus connected directly to the 405 is the processor local bus (PLB). A secondary bus is also implemented and is called the on-chip peripheral bus (OPB). The two buses are connected through a bridge.

The bridge imposes clock cycle latencies for accesses to peripherals connected to the OPB. The OPB is a slower bus implementation than the PLB. The PLB should be reserved for high-speed and high-pri-ority devices, while slower and lower-priority devices may be mapped onto the OPB. Each peripheral device must have a defined mode of operation on the bus; master, slave or both. The memory range for each peripheral device must also be defined. For this example all the peripherals will be memory mapped.

The FPGA device-level and board-level decisions for the peripherals are interrelated with design implementation factors such as FPGA device placement and orientation, the physical relationship to other components on the board, the I/O standards for each FPGA pin, the I/O bank architecture and any I/O assignment limitations.

The decisions regarding the implementation of the external peripheral interfaces and related internal logic placement associated with each peripheral must take into account the overall FPGA data-flow. This effort must optimize the flow of data to and from the processor to high-priority and high-speed peripherals.

Floorplanning is an important design activity that can guide the tools to achieve the desired device layout and preferred data path flow. High-bandwidth and high-speed interfaces should be given extra care. Additional information can be found i ***a***n Xilinx application note, XAPP653 3.3V PCI Design Guidelines.