In Part 2 in a series, Joseph Yiu, author of “The definitive guide to the ARM Cortex-M0,” describes the differences between the Cortex-M1 and the Cortex-M0 and how to port your software code base between them.
Both the Cortex-M1 and the Cortex-M0 are based on the ARM architecture v6-M, so the differences between the Cortex-M1 and the Cortex-M0 are relatively small.
Instruction Set. In the Cortex-MI processor, WFI, WFE and SEV instructions are executed as NOPs. There is no sleep feature on current implementations of the Cortex-MI processor.
SVC instruction support is optional in the Cortex-Ml (based on the design configuration parameter defined by an FPGA designer), whereas in the Cortex-M0 processor, SVC instruction is always available.
NVIC. SVC and PendSV exceptions are optional in the Cortex-Ml processor. They are always present in the Cortex-M0. Interrupt latency are also different between the two processors. Some optimizations related to interrupt latency (e.g. zero fitter) are not available on the current implementations of Cortex-MI processor.
System-Level Features. The Cortex-M1 has Tightly Coupled Memory (TCM) support to allow memory blocks in the FPGA to connect to the Cortex-M1 directly for high-speed access, whereas the Cortex-M0 processor has various low-power support features like WIC (Wakeup Interrupt Controller).
There are also a number of differences in the configuration options between the two processors. These options are only available for FPGA designers (for Cortex-M1 users) or ASIC designers (for Cortex-M0 microcontroller vendors).
For example, with the Cortex-M1 processor you can include both the serial wire debug and the JTAG debug interface, whereas Cortex-M0 microcontrollers normally only support either the serial wire or the JTAG debug interface.
Porting between the Cortex-M0 and -M 1
In general, software porting between Cortex-M0 and Cortex-M 1 is extremely easy. Apart from peripheral programming model differences, there are few required changes.
Because both processors are based on the same instruction set, and the architecture version is the same, the same software code can often be used directly when porting from one processor to another. The only exception is when the software code uses sleep features. Because the Cortex-Ml does not support sleep mode, application code using WFI and WFE might need to be modified.
There is also a small chance that the software needs minor adjustment because of execution timing differences.
At the time of writing, no CMSIS software package is available for the Cortex-M1. However, you can use the same CMSIS files for the Cortex-M0 on Cortex-Ml programming, because they are based on the same version of the ARMv6-M architecture.
Differences between the Cortex-M3 and -M0
The Cortex-M3 processor is based on the ARMv7-M architecture. It supports many more 32bit Thumb instructions and a number of extra system features.
The performance of the CortexM3 is also higher than that for the Cortex-M0. These factors make the Cortex-M3 very attractive to demanding applications in the automotive and industrial control areas.
Programmer’s Model. The ARMv7-M architecture is a superset of the ARMv6-M architecture. So it provides all the features available in the ARMv6-M. The Cortex-M3 processor also provides various additional features.
For the programmer’s model, it has an extra nonprivileged mode (User Thread) when the processor is not executing exception handlers. The user Thread mode access to the processor configuration registers (e.g., NVIC, SysTick) is restricted, and an optional memory protection unit (MPU) can be used to block programs running in user threads from accessing certain memory regions (Figure 21.3 below).
Apart from the extra operation mode, the Cortex-M3 also has additional interrupt masking registers. The BASEPRI register allows interrupts to of certain priority level or lower to be blocked, and the FAULTMASK provides additional fault management features.
Figure 21.3:Programmer’s model differences between the Cortex-M0/-M3.
The CONTROL register in the Cortex-M3 also has an additional bit (bit) to select whether the thread should be in privileged or user Thread mode.
The xPSR in the Cortex-M3 also has a number of additional bits to allow an interrupted multiple load/store instruction to be resumed from the interrupted transfer and to allow an instruction sequence (up to four instructions) to be conditionally executed.