Sonics’ New IP for Low-Power SoCs Patented

TOKYO — Sonics Inc., a vendor of on-chip interconnect technology based in Milpitas, Calif., has developed a new hardware-based IP block, a so-called “Intelligent Power Controller,” intended to help chip designers develop low-power SoCs.

The technology is designed to deliver power savings by the intelligent control of power to cores. The ability to keep cores switched off for longer periods of time, along with the ability to turn devices on and off more rapidly, will enable power savings over current solutions, according to Sonics.

The company revealed last week the issuance of patent 8,601,288 from the US Patent Office. Based on the patent, the Intelligent Power Controller enables SoC designers “to partition power domains and turn them on and off without software intervention for the most energy efficient chip implementation.”

The Intelligent Power Controller is a hardware-based IP, designed to sit in the middle of a system-on-chip architecture. Its function is to control power distribution and manage consumption problems in complex SoC designs.

In a phone interview with EE Times, Ray Brinks, senior vice president of operations at Sonics, said, “Power is always on top the list” of all the headaches for chip designers. “Every designer is scared to death of power problems.”

In pursuit of lower-power SoCs, chip designers have been taking various approaches.

They include adopting cutting-edge process technology (e.g., finer geometries, low-leakage memory. SOI), leveraging software (e.g., the use of power-aware operating system and apps, and power-aware memory allocation), developing new architecture that takes advantage of parallelism and memory architecture, and embracing designs built for high-level optimizations (power and clock gating, etc.).

Sonics says that its Intelligent Power Controller, fundamentally different from those known approaches, will complement them.

Brinks explained that the new hardware-based power management IP “operates independent of operating system and applications,” while it is also “adaptable” to chip loads, and is “visible” to chip mode. Further, it is “fundamentally reactive in single-digit clocks.”

Where power manager hardware sits in a complex SoC with multiple domains (Source: Sonics)

Where power manager hardware sits in a complex SoC with multiple domains (Source: Sonics)

Noting that today’s complex SoCs consist of many blocks, Brinks says a conventional SoC needs to wake up many on-chip blocks to ensure, for example, that it’s OK to change the voltage slew-rate. In contrast, Sonics’ Intelligent Power Controller can make the intelligent decision of awakening only one block — as quickly as a nanosecond, he explained.

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