Developers in communications and industrial/commercial digital applications often come across problems when implementing the connection between a high-resolution analog-to-digital converter (ADC) and an ASIC or FPGA. JEDEC has released a high-speed serial bus to increase productivity. Previously, connections used a low-voltage differential signaling (LVDS) differential bus. With up to 14 to 16 bits of parallel data from an ADC and a speed limitation of about 800 Mbits/s to 1.6 Gbytes/s maximum, the connection distance is severely limited and the printed-circuit board (PCB) layout is difficult.
The JESD204B standard interface defines high-speed serial interconnections that can severely cut pin count and interconnect lines to simplify high-speed data paths. If you’re looking to avoid routing multiple 12- to 16-bit differential lines in your next design, use ADCs and FPGAs with JESD204A/B. The interface circuitry in the ADC and FPGA uses standard ISO layers including physical, data link, transport, and applications layers. The physical layer (PHY) handles the serializer/deserializer (SERDES) function and the drivers. The data link layer provides an 8b/10b encoder/decoder and frame/lane alignment. The transport layer includes data framing and optional scrambling. The application layer handles the signal clocking and synching. Equalization at the receiver and pre-emphasis at the transmitter are options at the 12.5-Gbit/s speed level depending on connection length.
The original JESD204 interface introduced in 2006 defined a single differential lane 3.125-Gbyte/s path between two devices. In 2008, a revised JESD204A version supported multiple lanes of 3.125-Gbit/s serial data. The 2011 revised JESD204B specification boosted the data rate to 12.5 Gbits/s per multiple lanes. The reach at these speeds extends to 20 cm of standard FR-4 PCB material.
One of the first devices to use the JESD204B interface is Analog Devices’ AD9250 ADC (see the figure). This dual-channel, 14-bit, 250-Msample/s ADC targets applications such as software-defined radios and medical ultrasound. The interface reduces the pin count and connections from 14 differential pairs to just two pairs. It is designed to connect to selected Altera, Lattice, or Xilinx FPGAs that support the interface. FPGA vendors refer to the JESD204B interface as a GTX transceiver.
The AD9250 features 70.6 dBFS at 185-MHz amplitude input (Ain) and 250 Msamples/s, 88-dBc spurious-free dynamic range (SFDR) at 185-MHz Ain and 250 Msamples/s, IF sampling frequencies to 400 MHz, and 95-dB channel isolation/crosstalk. The power consumption of both channels at 250 Msamples/s is 711 mW with a 1.8-V supply. The package is a 7- by 7-mm 48-pin LF-CSP. A 170-Msample/s version is also available. Samples and production quantities as well as an evaluation platform are available now.
Another Analog Devices part that uses the JESD204B interface is the AD9671, an octal ultrasound analog front end (AFE). This device contains eight channels of LNA, VGA, 14-bit 125-Msample/s ADC, and a digital demodulator/decimator. To implement a typical 192-channel ultrasound system, 24 octal AFEs are needed. In previous implementations, there were 10 LVDS pairs needed per octal AFE for a total of 240 LVDS pairs. Using the AD9671 with the JESD204B interface, two CML pairs are needed per octal AFE for a total of only 48 CML pairs, an 80% reduction.
Samples of the AD9671 are available now, and full production quantities will be available in December of 2012.