Arm’s new 64-bit Cortex-A50 series embodies the ARMv8-A architecture (Fig. 1).
This platform will now be available from a number of vendors targeting the enterprise and small business markets.
Applied Micro’s X-Gene
(see Arm Joins The 64-bit Club)
was announced earlier this year.
The ARMv8-A platforms are upward compatible with the existing ARMv7 platforms allowing them to run existing 32-bit software.
This is comparable to the relationship between 32-bit and 64-bit x86 platforms.
The Cortex-A50 targets a wide range of applications and different incarnations will be optimized for these areas.
This includes high end enterprise applications to mobile devices such as smartphones and tablets where power efficiency is paramount given their battery-based power supplies.
Like other Cortex architectures, the Cortex-A50 is gaining a major following of hardware vendors including AMD.
The power efficient Cortex-A53 and the high performance Cortex-A57 (Fig. 2) are the first two in the Cortex-A50 series.
They are code compatible and differ in terms of architectural optimizations.
The Cortex-A50 supports a fixed length decoding scheme designed for low power implementation.
The Cortex-A50 can incorporate other Arm technologies like TrustZone security.
Of course, virtualization is part of the base architecture.
It is also designed to work with Arm’s latest Mali GPUs
(see Mobile GPU Architecture Supports Emerging Compression Standard).
Mali supports cache coherent interfaces providing a higher performance link between the GPU cores and CPU cores.
The Cortex-A50 series targets the latest chip technologies including 20nm and 14nm process technologies.
This obviously provides size advantages and the 64-bit Cortex-A53 core will be a quarter of the size of a Cortex-A9 when moving from a 32nm Cortex-A9 to a 20nm Cortex-A53 (Fig. 3).
Both chip cores are likely to be used in all the of the target markets but in different combinations and configurations.
Single core chips can provide high performance with a minimal power and size footprint while multicore versions can provide performance that can be utilized in
high performance computing (HPC) and server platforms.
A standard cache coherent interconnect links up to 16 cores together.
Arm’s big.LITTLE approach
(see Little Core Shares Big Core Architecture)
can be used to combine an Cortex-A57 and Cortex-A53 (Fig. 4)
This type of chip can target mobile applications such as smarthpones and tablets as well as other embedded applications.
Most vendors are likely to incorporate the usual peripheral complement in their 64-bit Arm chips but
AMD is taking a slightly different approach.
AMD recently acquired SeaMicro that had packed 768 Intel Atom cores
(see Server Packs 768 Atom Cores To Take On The Cloud)
into 10U rack.
This system employs AMD’s SeaMicro Freedom Supercompute fabric that implements a hypercube mesh network.
To date, the fabric has been used to link nodes that include the aforementioned Atoms as well as AMD Opteron and Intel Xeon processors.
This was done using a SeaMicro fabric chip linked to each processing chip.
Future AMD Arm chips will incorporate the fabric support into the processor chip.
While AMD does not license the fabric for inclusion in chips it will likely make these chips available so designers could create large arrays.
HPC systems like this would be very compact and power efficient.
The approach would eliminate a chip and reduce a node to the processor and its external memory chips.
Such as chip might also take AMD’s APU (application processing unit) approach that combines the CPU and GPU components
(see APU Blends Quad Core x86 With 384 Core GPU).
Another possibility not yet discussed would be chips that would employ HyperTransport instead.
This would allow existing AMD motherboards to support the chips.
Cortex-A50 represents a major shift in Arm’s portfolio.
It also puts Arm in direct competition with Intel’s server side of the business.
Next year looks to be a very interesting time for designers as well as users.