Dealing with multi-Vt & multi-voltage domain timing/temperature inversion challenges

Scaling down CMOS technologies to 40 nm and below is imposing new challenges for physical design engineers relating to timing closure in their designs. In higher technology (90 nm and above), process, voltage and temperature (PVT) corners with the highest temperatures used to be the worst locations for synthesis.

Dealing with multi-Vt & multi-voltage domain timing/temperature inversion challenges
Definition of Terms


Whereas at 90 nm and above, the delay times of a cell increases as temperature increases (Figure 1 below). But as we move to lower technology nodes (65 nm and below), it is necessary for designers to pick the libraries corresponding to the lowest temperature PVT because of temperature inversion effects where the delay of the cell actually decreases with increase in temperature.

Dealing with multi-Vt & multi-voltage domain timing/temperature inversion challenges


Figure 1. Delay Variation with temperature

To confirm this effect in our designs using 40nm technology, we did few experiments. In this paper we will discuss those results and a few other factors associated with the temperature inversion effect. Analysis was done at cell level on a single inverter and the above behavior was confirmed (i.e. higher delay at lower temperature) as shown in Figure 2 below, with a Standard VT (SVT) library and core voltage of 1.1V.

Dealing with multi-Vt & multi-voltage domain timing/temperature inversion challenges


Figure 2. Delay Characteristics of single stage inverter (To view larger image, click here)

In the above analysis, delay of the cell was measured at different temperature values. But the transition on the input and load at the output of inverter they often are assumed to be the same. So, the above analysis is not accurate as in reality, both input transition and input load are bound to change with temperature i.e. transition and input load increases with increase in temperature as shown in Figure 3 below.

Dealing with multi-Vt & multi-voltage domain timing/temperature inversion challenges


Figure 3. Variation of input capacitance and input transition with temperature. (To view larger image click here)

The delay of a cell is direct function of both input transition and output load. As shown in Figure 3, input transition and input capacitance are lesser at lower temperature, so delay of the cell at lower temperature can actually be less as compared to higher temperature when used in real SoC designs because the input capacitance of cells will actually contribute to output load of its driver.


To explain the above reasoning, the simulations needed to be carried out on a chain of inverters connected in series. We used 5 inverters in series as shown in Figure 4 below.

Dealing with multi-Vt & multi-voltage domain timing/temperature inversion challenges


Figure 4. Delay Characteristics of chain of inverter at 1.1V. (To view larger image, click here)

In this case, the following was observed:


1. A constant value of input transition and output load across temperature is applied at the input and output of the circuit respectively.


2. Delay of the middle (third) inverter is measured by varying the temperature only. The variation in input transition and output load of this third inverter will automatically come into calculations. Here, the trend line completely reversed as compared to that observed in a cell level analysis shown in Figure 4 above.

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