Booting an Intel Architecture System, Part I: Early Initialization

The boot sequence today is far more complex than it was even a decade ago. Here’s a detailed, low-level, step-by-step walkthrough of the boot up.

Taking a lot of little steps along a path is a good analogy for understanding boot flow in Intel Architecture-based systems. The minimum firmware requirements for making a system operational and for booting an operating system are presented in this article. The vast majority of systems perform these steps in this article to do a full or cold boot. Depending on the architecture of the BIOS, there may be multiple software phases to jump through with different sets of rules, but the sequence for waking up the hardware is, at least in the early phases, very much the same.

Hardware Power Sequences: The Pre-Pre-Boot

When someone pushes the power button, the CPU can’t simply jump up and start fetching code from flash memory. When external power is first applied, the hardware platform must carry out a number of tasks before the processor can be brought out of its reset state.

The first task is for the power supply to be allowed to settle down to its nominal state. Once the primary power supply settles, there are usually a number of derived voltage levels needed on the platform. For example, on the Intel Architecture reference platform the main input supply is a 12-volt source, but the platform and processor require voltage rails of 1.5, 3.3, 5, and 12 volts. Voltages must be provided in a particular order, a process known as power sequencing. The power is sequenced by controlling analog switches, typically field-effect transistors. The sequence is often driven by a Complex Program Logic Device (CPLD).

Platform clocks are derived from a small number of input clock and oscillator sources. The devices use phase-locked loop circuitry to generate the derived clocks used for the platform. These clocks take time to converge.

It is only after all these steps have occurred that the power-sequencing CPLD can de-assert the reset line to the processor, as illustrated in Figure 1. Depending on integration of silicon features, some of this logic may be on chip and controlled by microcontroller firmware that starts prior to the main processor.

Booting an Intel Architecture System, Part I: Early Initialization

Figure 1: An overview of power sequencing.

A variety of subsystems may begin prior to the main host system.

The Intel Manageability Engine (ME), available on some mainstream desktop and server-derived chips, is one such component. The main system firmware does not initialize the devices composing the ME. However, there is likely to be some level of interaction that must be taken into account in the settings of the firmware, or in the descriptors of the flash component, for the ME to start up and enable the clocks correctly. The main system firmware also has the potential to make calls and be called from the ME.

Another example is micro engines, which are telecommunications components used in the embedded-systems world. Micro engines have their own firmware that starts independently of the system BIOS. The host system’s BIOS must make allowances for them in the Advanced Configuration and Power Interface (ACPI) memory map to allow for proper interaction between host drivers and the micro-engine subsystem.

Once the processor reset line has been de-asserted, the processor begins fetching instructions. The location of these instructions is known as the reset vector. The reset vector may contain instructions or a pointer to the starting instructions in flash memory. The location of the vector is architecture-specific and usually in a fixed location, depending on the processor. The initial address must be a physical address, as the Memory Management Unit (MMU), if it exists, has not yet been enabled. The first fetching instructions start at 0xFFF, FFF0. Only 16 bytes are left to the top of memory, so these 16 bytes must contain a far jump to the remainder of the initialization code. This code is always written in assembly at this point as there is no software stack or cache RAM available at this time.

Because the processor cache is not enabled by default, it is not uncommon to flush cache in this step with a WBINV instruction. The WBINV is not needed on newer processors, but it doesn’t hurt anything.

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