Basics of SoC I/O design: Part 2 – Hot swap & other implementation issues

Having dealt in Part 1 with some of the basics of SoC I/O pin assignment, in this second part we will deal with a variety of implementation issues, including hot swap, threshold voltages, interrupts, pin assignments and Interfacing with the devices being operated at voltage other than SoC’s core voltage


Hot Swap

Systems like industrial and network equipment requires live insertion or hot swap to avoid long start-up operation or other down time related inconveniences. Hot Swap usually means that an electronic module can be removed and then reinserted into a system while the system remains under power. The assumption is that the removal of the module and reinsertion will cause no electrical harm to the system.


To deal with this scenario, the interconnecting IOs must have what is called hot swap capability. This basically means that IO pins must offer a high impedance drive mode even if the module is not powered.


Normal GPIOs generally come with a limitation that the voltage input on it cannot be greater than the Vdd of the device. This is due to the ESD diodes on the IOs which start conducting when the IOs are higher voltage than the Vdd, as discussed earlier.


Certain SOCs comes with special IOs which have an ability to Hot swap. These pins can connect to another system that is powered even when the device having the pins is not powered. The unpowered device can maintain a high impedance load to the external device while preventing itself from being powered through an IO pin’s protection diode


In designs that would have a requirement to be part of a plug and play arrangement and requires a hot swap, the system designer should consider the case while part selection. The number of these hot swappable IOs required is another consideration the designer would have to look into because hot swap capability is available only few IO lines in device due to design overhead to implement them.

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Threshold voltages

Input threshold voltage for any pin is characterized as the minimum input voltage that will be considered as logic High and maximum input voltage that will be considered as Low. Though most of the digital devices have CMOS drive level now a days, there are still many devices available which have other output levels like LVTTL (Low Voltage Transistor to Transistor Logic).


To deal with such I/o level mismatches, systems need the use of some interface devices that have selectable input threshold. To avoid the use of such external level translators, one must consider selecting an SoC/Controller which has i/o input threshold compatible with other devices.


Some of the SOCs have IOs that have programmable threshold where user is not restricted to standard threshold voltages. Changing the threshold is nothing but changing the reference voltage to the hysteresis comparator. Based on this functionality these pins can now be considered as simple comparators. There might be cases in the design when this functionality can be helpful.



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