Basics of core-based FPGA design: Part 3 – Picking the right core options

There are a number of system design factors requiring consideration when implementing an FPGA processor. Some of those factors include the use of co-design, processor architectural implementation, system implementation options, processor core and peripheral selection, and implementation of hardware and software.


Embedded software development has the potential to consume 50% or more of embedded processor design schedules. Thus, it is important to have and follow a cohesive hardware and software development flow on a rapid system development project. This important collaboration between hardware and software design teams can help to streamline and parallel development.

The parallel development of hardware and software is called ***a*** co-design. Effective co-design is important to implementing an efficient rapid system development effort. Co-design has the potential to impact many of the elements associated with embedded project development, supporting increased system flexibility and reduced schedule.

The system design tool chain can be critical to efficient co-design. The tool chain is the collection of hardware and software tools used for design entry, simulation, configuration and debug. An effective tool chain will provide a high level of interaction and synchronization between the hardware and software tool sets and design files. Figure 14.3 below illustrates the interactions and relationships between the two tool flows.

Basics of core-based FPGA design: Part 3 – Picking the right core options

Figure 14.3. FPGA co-design flow

In evaluating co-design tools, two of the most important factors affecting the selection are tool maturity and ease of use. The embedded FPGA processor software tool chain should include a software development kit (SDK), which supports efficient development of low level drivers, and a range of operating system implementations. The hardware tools should support the efficient integration of IP and hardware and software debug synchronization. Some desirable co-design tool characteristics are presented in the following list.

Desirable Co-Design Tool Characteristics 

1) Automated tools that hide the details but keep them accessible

– Intelligent tool ***a***s must understand all details of the platform options, but provide a high level of abstraction to streamline design and synchronize hardware and software components.

– Tool sophistication targets design co ***a***mplexity

2)  Tool functions that can accelerate development

– Wizards and generators

3) Easy to learn and use

– Intuitive user-friendly interface

4)  Supports complete control of the design

– Robustness to change/control without the loss of flexibility

5) Powerful integrated debug capabilities 

6) Integrated baseline control capability

Processor architecture alternatives

Since the RISC architecture is arguably the most implemented processor architecture, this book will limit discussions to the RISC architecture. When designing with a RISC-based processor, there are many architectural considerations affecting hardware and software design optimization. This section will highlight some of the RISC architectural considerations.

Achieving optimal system performance (required throughput) is a critical element of embedded processor design implementation. Optimal system performance is accomplished by informed design implementation of the hardware and software. Processor architecture is a critical factor that determines system performance. Understanding the architecture of the processor selected will assist the design team in making informed design decisions.

The RISC architecture increases processor performance by imposing single cycle instruction execution. This point is clarified by considering Equation 14.1 below,  a common equation used to derive a processor’s performance. If the number of cycles per instruction are reduced in this equation, the processor performance is increased.

However, this increase in performance comes as a consequence of an increase in the number of instructions required to implement a software program, and thus an increase in the software program size. The result of the larger software program size is an increase in the number of external memory operations, which serves to reduce system performance.

Factors that influence system performance optimization include: processor core implementation, bus implementation and architecture, use of cache, use of a memory management unit (MMU), interrupt capability, and software program flow.

Basics of core-based FPGA design: Part 3 – Picking the right core options

Equation 14.1. Basic RISC Processor Formula

The processor core is responsible for the overall flow and execution of a software program. Common processor core elements include control, execution and temporary storage units. The load/store unit provides program control and instruction dispatch to the execution units.

The processor core incorporates a branching unit to control execution flow of the software program. An important feature of the branching unit is branch prediction. Branch prediction is used to minimize pipeline stalls by predicting the next logical path in the execution flow.



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