As we move to lower process technology transistor-size nodes, probe requirements from different vendors are becoming major hindrances to meeting targets for die size and for achieving parallelism in probing. Sometimes it is necessary to leave spaces in the pad ring to meet side pitch requirements. Probe vendors have specific pitch requirements but due to shrinking technologies, pad geometries are decreasing. For example, in 90 nanometer CMOS (cmos090) technology, the minimum pad pitch is 56 micrometers (μm), while the vertical probe pitch requirement is 80 μm. This forces us to have extra spaces between adjacent test or electronic wafer sorting (EWS) pads. In this paper, we present the various techniques a designer can use to meet all probe requirements for parallelism without wasting die area. We also briefly touch on the Corner Keep Out rules and side pitch rules and their impacts on pad ring design.
Probing requirements: Corner Keep Out
Corner Keep Out zones are required to meet the x4 parallelism on wafer probe. Here, we are taking an example of cmos090lp pad structure to explain the concept in Figure 1. A requirement of 170 μm meets the specifications of 90% of the vendors for x4 probe. The rule says that the probe axis of the first probe pad on one side should be a distance of 170 μm from the innermost probe axis of the adjacent side, and vice versa. To meet x4 probe, we need to satisfy the rule on all four sides of the pad ring. To meet x2 probe, we need to satisfy the Corner Keep Out zone on at least one side of the pad ring, i.e., the top and bottom row of pads can extend further into the corner than the left and right sides, OR the left and right side row of pads can extend further into the corner than the top and bottom.
As shown in Figure 1, for example, if the corner size is 207×209.4 μm and pad width is 56 μm, we need to avoid placing any probe pad for at least 391 μm from edge of the die. This is a big limitation, which challenges the designer to look for other opportunities to meet this requirement.
Figure 1: Corner Keep Out Zone
Probing requirement: minimum side pitch
This is the most common limitation one faces while designing a pad ring. The requirements for pad pitch and probe pitch are not the same. For cmos090lp IO library, the pad pitch is 56 μm, while 80 μm is required for vertical probes, as shown in Figure 2 below.
Figure 2: Minimum side pitch and probe pitch
Targeting the Corner Keep Out zone requirement
In today’s world, we design various SoCs in different phantom parts. A single die is packaged in different flavors to save engineering design costs and to be competitive in the market in terms of pricing. We can use the same concept in our designs. Generally, all the base package pads are supposed to be available for probing. So, one can place all non-EWS probe pads of higher pin-count packages in these Corner Keep Out zones. This will fully utilize the area which otherwise is wasted. One needs to carefully design a pad ring so as to meet all interface specifications, bonding requirements, etc. before using the Corner Keep Out zone.
For example, we worked on a 90nm SoC that had two flavors, 196MBGA and 256MBGA. All 196MBGA pads were available at probe while all non-probe 256MBGA pads were placed at the corners. Please refer to Figure 3, where pads in the circle are all 256MBGA pads, placed at the corner on the right side.
Figure 3: An approach to meet Corner Keep Out rule
Targeting minimum side pitch requirement: placing EWS pads alternatively
Electrical Wafer Sort (EWS) or wafer probing is done in various stages, which we can call EWS1, EWS2, and so on. Basic tests like ATPG are included in EWS2, while flash testing and others are generally included in EWS1. EWS pads are actually a subset of all functional pads. A designer can work on test pin muxing looking at the pad placement. In this approach, pad placement is done before the test pin muxing is decided. The test pin muxing or assigning of EWS pads (Scan Ins, Scan Outs, etc.) can be done on alternative pads in the pad ring. This will eventually meet the Side Pitch requirement between two probe pads. For example, if three functional pads are placed adjacent to each other on the basis of pad pitch, one can assign EWS pads on alternate pads, i.e., pad #1 and pad #3. Please refer to Figure 4 for further explanation.
Figure 4: Assigning Scan Ins to alternate pads
The Scan Ins highlighted in Figure 4 represent the approach of assigning EWS pads to alternate functional pad, SI1, SI2, SI3, etc. are muxed on GPIO, GPIO, and GPIO respectively.