A brief primer on embedded SoC packaging options

With shrinking technology, voltage levels are being reduced, lowering noise margins required to enable a clean design from a signal integrity perspective. Higher operating frequency requirements further complicate design closure. Semiconductor packages are a quintessential piece of the signal integrity puzzle.


This article addresses the basics of packaging such as types of packages and their advantages and disadvantages, future trends, and factors to be considered while choosing a package.


Need for Packaging Bare Die

Silicon chips are very delicate, even a tiny speck of dust or drop of water can hinder their function. Therefore, silicon chips are protected by encapsulating or packaging them. However, packaging has its own set of limitations. Some packaging considerate are:


* Connections for signal lines in and out of the silicon chip.

* Connections for the power lines that power the circuit on the chip.

* Dissipation of heat produced by the chip.

* Mechanical connection of chip to a board or other devices.

* Protection from environmental influences.

* Protection from mechanical damage.

* Thermal expansion.


Trends in Packaging

Today SiP (System in Package) has begun to capture the VLSI market where multiple dies are integrated into a package to create a large scale system. The semiconductor industry is under increasing pressure to reduce power, down-size devices, leverage advanced technology and create multi-function devices. Semiconductor packaging must keep pace.


A few improvements which have already been noticed on this front are: increasing the number of pins, decreasing package size, and increasing circuit density so that more and more devices can be accommodated in a smaller area. Going forward, the demand for new packages with even greater sophistication will drive package innovation (Table 1 below).

A brief primer on embedded SoC packaging options


Table 1: Broad classification of different types of packages

The industry-wide roadmap for IC packaging (Figure 1, below) has been to reduce size and increase circuit density.


With this in mind, since inception, the industry has gradually moved from QFP to BGA package and now with further miniaturization, high frequency operation, and a demand for more and more functionality in a still smaller area, it’s time for new innovation to follow in the packaging world.

A brief primer on embedded SoC packaging options


Figure 1. IC Packaging Roadmap (Courtesy: Renesas Electronics)

SoC technology allows a system having several circuit functions to be built on a single silicon chip. But with increasing need for more functionality and shorter design cycles, it has become difficult to create SoCs independently.


As noted in Figure 2 below, SiP makes use of packaging technology and allows for the creation of a large scale system in one package by connecting already existing high performance SoC and multiple dies like high precision analog die, high capacity memory, etc.

A brief primer on embedded SoC packaging options


Figure 2. Example of SiP structure using five stacked chips. (Courtesy: Renesas Electronics)

PoP (Package on Package) is another trend. In PoP, logic functions, memory, etc. are designed and packaged as separate SoCs and then the selected parts are attached (stacked) to realize a large system.


It is possible to select among a range of memories and other blocks available and then encapsulate all of the selected devices within a mother package (TOP Package).


This allows for a larger market base for the products and also offers greater flexibility (for example, the same PoP can be made with different size memory chips). The demand for such packages is very high for mobile products.


SiP uses the latest technology and offers wide variety, each having its own merits and demerits. A brief outline is shown in Table 2 below below:

A brief primer on embedded SoC packaging options


Table 2. Pros and cons of various SiP options


Concerns in Packaging

With higher packaging density, the two most common problems faced by package designers and SI engineers are thermal concerns and electrical noise concerns. Shown in Table 3 below is a summary of some of those challenges:

A brief primer on embedded SoC packaging options


Table 3. Packaging challenges and market drivers


Package thermal concerns

The quality of the package is determined by how well it dissipates the heat generated by the silicon devices encapsulated within it. Heat generated may seriously impair the die’s performance, safety and reliability. Heat dissipation occurs in three ways viz. conduction, convection and radiation, as outlined below.


* From the surface of the package into the atmosphere (radiation)

* From the external pins to the printed wiring board and then into the atmosphere (conduction)

* From the heat source to the sides of the package (convection).


One way to achieve good heat dissipation is to decrease the thermal resistance of the semiconductor devices. The thermal resistance of the package is almost entirely determined by the:


* Structure of the Package

* Size of Package

* Air flow rate

* Chip dimension


Heat dissipation in packages occurs mostly through conduction.


Packaging electrical concerns

With continuous reduction in operating voltage as a means to lower power requirements, noise margins have also decreased, leaving the devices increasingly susceptible to electrical noise.


More so, with miniaturization in packaging it has been of prime concern to preserve the signal integrity. ‘Power supply noise’ and ‘Signal noise’ are the two types of electrical noise that need to be taken care of.


Power Supply noise
SSN (Simultaneous Switching Noise): When a large number of transistors and I/Os switch together, it causes a substantial change in the supply voltage and ground voltage. This induces switching noise in the devices which share the same power and ground planes. If not tackled, it can ruin the system.


Signal Noise
Cross-talk noise: Whenever signal lines (busses) run in parallel for a long distance they influence each other because of inductive and capacitive coupling. A change in one signal line may induce unwarranted change in another.


Reflection noise: An IC is composed of many components like semiconductor devices and interconnects like vias, balls, etc. each having its own characteristic impedance. Whenever a signal takes a path with different characteristic impedances, at every node there is some reflection. These reflections cumulatively may be enough to cause serious signal integrity issues.


Attenuation: When the signal has to travel long distances it suffers from attenuation because of path resistances and other influences. It is of serious concern in high speed ICs.


Jitter: In digital circuits, all of the signals are in reference to clock signals. The deviation of the digital signals due to reflection and other reasons amounts to jitter.


References

[1] Freescale Packaging White Paper

[2] www.renesas.com/prod/package/what.html

[3] www.digikey.com/


The authors all work for Freescale Semiconductor on signal integrity problems in embedded IC design where Deepak Behera is a Design Engineer; Sumit Varshney is a Sr. Design Engineer with expertise in physical integration and package designing and signal integrity; Sunaina Srivastava is a Sr. Design Engineer with experience in embedded systems and board design; and Swapnil Tiwari is a Design Engineer with experience in microwave antenna design.

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