With the release of JEDEC’s JESD204B serial data interface, designers are abandoning the 14- to 16-bit parallel differential low-voltage differential signaling (LVDS) connections from analog-to-digital converters (ADCs) to FPGAs, DSPs, or some ASICs. This reduces the number of lines and lengthens the runs for a simpler circuit. Recently, Texas Instruments adopted the JESD204B interface for its 16-bit ADS42JB69 ADC.
The JESD204B interface is an open standard defining high-speed serial interconnections that greatly reduces pin count and interconnect lines. The original JESD204 interface introduced in 2006 defined a single differential lane 3.125-Gbyte/s path between two devices. In 2008, JESD204A defined multiple lanes of 3.125-Gbit/s serial data. In 2011, JESD204B increased the data rate to 12.5 Gbits/s per multiple lanes. The reach at these speeds extends to 20 cm of standard FR-4 printed circuit-board (PCB) material. The embedded output data clock eliminates the need for bus line matching, greatly simplifying the interface between chips and reducing board space.
The ADS42JB69 is a dual 250-Msample/s 16-bit ADC, and 14-bit pin-compatible versions are available as well. Both use the JESD204B interface. The 16-bit ADS42LB69, which uses a parallel LVDS interface, is also an option.
The ADS42JB69 is flexible in system design because it incorporates all three JESD204B subclasses-0, 1, and 2-allowing multi-device synchronization between data converters. This chip also supports the JESD204B specification for deterministic latency that provides fixed transmission delay with or without the use of an external timing signal. And, it’s backward compatible with the JEDS204A standard.
Using a 170-MHz IF, the ADS42JB69’s spurious-free dynamic range (SFDR) is 89 dBc. The SFDR excluding harmonic distortion is 100 dBc. The signal-to-noise ratio (SNR) is up to 74.9 dB relative to full scale. The channel isolation is 100 dB. Its high-impedance analog input buffer with programmable full-scale range simplifies input filter design and drive circuitry. Power consumption is 775 mW per channel.
The LMK04828 clock jitter-cleaner supports JESD204B clocking (see the figure). Two voltage-controlled oscillator (VCO) cores operate at 2.5 GHz or 2.9 GHz. The jitter is less than 100-fs RMS at 245.76 MHz. The chip also generates the subclass 1 SYSREF companion signals to provide timing synchronization for up to seven subsystem JESD204B components.
Samples of all these parts are available. Full production of the ADCs is expected in the second quarter of 2013. Evaluation modules are also available for all devices.