16 Core Chips Target Enterprise Servers


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Date Posted: November 05, 2012 04:07 PM


AMD has released its Opteron 6300 series (Fig. 1) that can deliver up to 16 cores based on
AMD’s Piledriver architecture.
The Opteron 6300 delivers 40% better performance/watt compared to the previous generation while providing even better power management features.


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Figure 1. The Opteron 6300 delivers its cores in pairs that now include dedicated floating point units for each core.


Each chip has four HyperTransport 3.0 links that deliver up to 6.4GTransfers/s per link.
This allows direct connections on a multichip motherboard with up to four sockets.
Each chip has access to memory provided by the other chips within the system.
Each chip has four DDR3 channels that handle memory up to 1866 MHz.








Scalability

Up to 4 sockets with up to 16 cores

Memory

4 DDR-3 memory channels: up to 1866 MHz memory


Up to 1.5 Tbytes capacity in 4P configurations

Frequency

Up to 3.5 GHz base frequency


Up to 3.8 GHz using AMD Turbo CORE technology

Cache

L1 – 16 Kbyte data per core + 64 Kbyte instruction per module L2 – 1 Mbyte per core


L3 – 16 Mbyte per socket

I/O

Four x 16 HyperTransport technology 3.0 links at up to 6.4GTransfers/s per link

Power

85W to 140W TDP


The system architecture and socket are the same as for the Opteron 6200 allowing the new chips to be used with existing motherboards.
The Opteron 6300 cores have their own floating point support that deliver better performance with applications that heavily utilize floating point data.


Pricing starts at $293 for the eight core, 2.8 GHz Opteron 6320 with a 115W TDP.
The all core Turbo frequency for this chip is 3.1 GHz while the max Turbo core frequency is 3.3 GHz.
The top end 16 core, Opteron 6386SE pushes the max Turbo core frequency to 3.5 GHz.


AMD has been working with third parties to improve the performance of compilers and Java virtual machines to take advantage of the new architeCture.
This provides improvements for the current and prior generation of processors as well.


Some of the “Piledriver” instructions used in these optimizations include the FMA3 floating point fused multiply add instruction,
the F16c floating point value conversion instruction and the BMI bit manipulation instruction.
These are also supported on Intel’s Xeon chips.
The first is used for matrix operations especially for digital signal processing applications.
The second is handy for conversion between 32-bit single precision and 16-bit half precision used in many multimedia algorithms.
The BMI instruction simplifies bit manipulation in general.
AMD has also included the TBM trailing bit manipulation instruction to extend the BMI features.


AMD’s Opteron line challenges Intel’s Xeon in the enterprise server market but the best or most cost effective chip will depend upon the application mix and system configuration.
Intel’s chips employ HyperThreading versus AMD’s used of individual cores.